Racing BIKE: Improved Polynomial Multiplication and Inversion in Hardware

BIKE is a Key Encapsulation Mechanism selected as an alternate candidate in NIST’s PQC standardization process, which performance plays significant role the third round. This paper presents FPGA implementations of with best area-time reported literature. We optimize two key arithmetic operations, are sparse polynomial multiplication and inversion. Our multiplier achieves time-constancy for polynomials indefinite Hamming weight used BIKE’s encapsulation. The inversion based on extended Euclidean algorithm, unprecedented current implementations. optimized design results 5.5 times faster generation compared to previous Fermat’s little theorem.Besides optimizations, we present united hardware shared resources sub-modules among KEM functionalities. On Xilinx Artix-7 FPGAs, our light-weight implementation consumes only 3 777 slices performs generation, encapsulation, decapsulation 797 ?s, 443 6 896 respectively. high-speed requires 7 332 three operations 1 672 132 892